Description
It can be used to compensate for both static and dynamic artefacts. On the static side, the same correction is applied to all frames. It can be used, for examples, to correct geometric aberrations, to perform image rectification, or to spatially align multiple sensors. Such free-form image warping are typical pre-processing steps for numerous high-level computer vision algorithms, as stereo reconstruction, metrology or multi-sensors fusion.
On the dynamic side, the IP can be used, for example, as the final stage of some motion compensation (video stabilization) systems. In this case, each of the output frames is generated from its own set of warping coefficients, hence dynamic correction.
A combination of static and dynamic warping can also be performed (example: simultaneous image rectification and motion compensation).
The core is 100% hardware (i.e. no CPU involved), fully pipelined (a new pixel every clock cycle), has very low latency and needs no external memory.
Features
- Primarily intended for 1080P60 video
- Arbitrary frame size and warping range only limited by available FPGA/SoC resources and necessary clock rate
- Supporting both static and dynamic arbitrary free-form warping of input video stream
- Fully pipelined. Ready for a new input pixel on every clock cycle
- Low-latency (i.e. a fraction of a frame) almost exclusively depending on the specified warp range and frame size
- CPU-free processing (CPU is only used for housekeeping)
No need for external memory.
Support provided by INO at IPSupport@ino.ca
Notes:
- For a complete list of supported devices and configurations, see the Vivado IP Catalog and associated FPGA Datasheets.
- The IP core is delivered as an IP-XACT packaged IP, and comes with sample hardware and software projects for the purpose of demonstration.
- Simulation testbench is not provided.
